Genesis

Genesis™ is an integrated methodology, flow, and tool framework for creating models of semiconductor intellectual property (IP) blocks and subsystems.

Genesis is designed to be simulation standard independent and support any target user simulator. However, the default target simulator standard supported by Genesis is the SystemC/TLM industry standard by IEEE Standard SystemC 1666™-2005, OSCI SystemC 2.2, and SystemC TLM 2.0.1. The Genesis baseline default flow provides full support for model deployment to both the VLAB OSCAR SystemC/TLM simulation library and the OSCI OSCI SystemC 2.2 reference simulation library.

Genesis supports the entire model creation life cycle, from model specification, through model creation, test, to deployment to a virtual platform environment. It offers increased productivity and quality, shorter development lifecycles, and automated reuse across multiple simulation environments.

Genesis offers a description language to capture design IP structure and partial functionality. As a result, any ambiguity and confusion that may be present in traditional native language design specifications is avoided. Genesis also provides interoperability with the IP-XACT™ standard and can be customised for any other representation format.

Genesis provides significant productivity improvements compared to working in a native simulation environment due to its established modelling methodology and flow, as well as its rich modelling libraries. Part of our early success was built on this advantage — we are now offering the same benefit to all of our customers.

Genesis provides unique separation between design IP (intrinsic design behaviour and interfaces) and implementation IP (simulator specific implementation). Users of Genesis spend most of their time crafting and verifying the design IP, and relatively little on added value in implementation IP. In fact, Genesis models are easily portable across multiple simulation environments, including industry standard SystemC®, at a great benefit to overall return on investment for model creation.

Genesis uses the model description to automatically generate code, documentation and a testbench. The user simply needs to fill in model behaviour code and write tests against the design requirements.

The Hardware IP Modelling Toolbox™ provides support required for modelling Hardware IP blocks and subsystems. It offers convenient and backplane independent modelling objects and APIs for blocks, ports, buses, attributes, and much more.

Where applicable, the Genesis supports existing ESL standards. The toolbox can be used to produce models fully compatible with IEEE Standard SystemC 1666™-2005 and the OSCI SystemC 2.2 reference implementation, as well as the latest SystemC TLM 2.0.1 transaction level modelling standard.

The Genesis enables your virtual models to be always distributed to third parties in binary form, thus protecting your valuable IP and enabling new ESL business models. In particular, models can target any SystemC compatible simulation environment without the need to be rebuilt from source.